There are many techniques available for clock synchronization, however, all practical techniques fall into two basic schemes; (1) a resonator which is excited by rising and falling edges of received data and (2) a phase-locked loop which servos the clock to a fixed phase with respect to the rising and falling edges of the input data.
The resonator based scheme has two basic problems. First, the exact throughput delay of the resonator system is critical because signal detection, deciding between a "1" and "0", is done in a separate stage which utilizes the recovered clock. Keeping the throughput delay constant is difficult because of "slow" effects such as temperature and "fast" effects such as delay variation introduced by input amplitude variation. Second, the resonator circuit has a specific resonance which restricts the tunability of the click recovery circuit to the pass band of the resonant circuit. It is generally unlikely that the incoming data signal exactly matches the natural resonance of a high Q resonator, particularly since the resonant frequency tends to shift with aging. This mismatch causes two undesirable effects. First, the clock output can be severely attenuated because the roll off of the resonator response characteristic is fairly steep. Second, in the absence of data edges, the clock output frequency will drift toward the natural resonant frequency of the circuit curing "flywheeling".
The phase-locked loop (PLL) approach does not exhibit the timing problems mentioned above since signal detection and clock recovery are all performed in one loop. Furthermore, phase-locked loops possessing a narrow loop bandwidth, equivalent to high Q, and relatively wide tuning range are easily designed and are more tolerant to component parameter variations. A PLL using a "sample and hold" type phase detector with a narrow loop bandwidth will "hold" its frequency when no transitions occur because the phase detector does not drive the VCO in either direction. The most practical approach to a high frequency PLL circuit is an analog approach because high resolution digital PLL circuits require impractically high master clock frequencies.
Two prior art circuits of the closed-loop clock extraction type are the "Early-Late Gate Synchronizer" shown in FIG. 1, and "Signal Detection Apparatus", shown in FIG. 2 which corresponds to FIG. 3 of U.S. Pat. No. 4,535,454. The Early-Late Gate Synchronizer is a completely analog clock extraction loop which utilizes two integrate-and-dump filters for signal detection and phase error signal generation, while the Signal Detection Apparatus utilizes a pair of edge-triggered D flip-flops for this purpose.
The primary drawback of the "Early-Late Gate Synchronizer" is its need for an integrate-and-dump filter which is capable at operating at high speeds. The Signal Detection Apparatus circuit of FIG. 2 is capable of operating up to the maximum clock frequency of the edge-triggered D flip-flops, which is in general much higher than that of currently available integrate-and-dump filters. However, this loop is not capable of producing the beat notes required for unaided frequency acquisition.